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technical note motor driver ic series fo r tape record systems 2 in 1 motor driver for vtrs bd6903efv, bd6904fp description the bd6903efv and bd6904fp single chip 3-phase full-wave motor driv ers integrate soft switching for low noise sensorless drivin g as well as a pg amplifier that enables pg/fg output, making them ideal for use in cylinder motors and l oading motors in non-portable vi deo tape recorders (vtrs). features 1) cylinder motor driver 2) sensorless 3-phase full-wave soft switching drive system 3) dmos output 4) built-in startup circuit 5) built-in pg amp 6) 3-value common pg/fg output 7) loading motor driver 8) three mode output (forward, reverse, brake), depending on control logic input 9) dmos output 10) built-in thermal shut-down (tsd) circuit applications vtrs product line parameter bd6903efv bd6904fp control block (vcc) 4.5 5.5v 4.5 5.5v control block (vg) vm+3 19v vm+2 19v power supply voltage output block (vm) 9 13.5v 9 14v 800ma 800ma maximum output current (cylinder) (loading) 1000ma 800ma current limit voltage no 295mv reversible operation mode forward rotation, reverse rotation, brake forward rotation, reverse rotation, stop, brake number of reversible control input pins 1pin 2pins package htssop-b20 hsop-25 ver.b oct.2005
2/16 absolute maximum ratings (ta = 25c) bd6903efv bd6904fp parameter symbol limit limit unit applied voltage vcc 7 7 v applied voltage vm 15 15 v applied voltage vg 20 20 v power dissipation pd 1000 *1 1450 *2 mw operating temperature range topr -20 +75 -20 +75 storage temperature range tstg -55 +150 -55 +150 maximum output current (cylinder block) iomax1 800 *3 800 *3 ma maximum output current (loading block) iomax2 1000 *3 800 *3 ma junction temperature tjmax +150 +150 *1 reduced by 8.0 mw/ over 25c when mounted on a glass epoxy board (70 mm 70 mm 1.6 mm). *2 reduced by 11.6 mw/ over 25c when mounted on a glass epoxy board (90 mm 90 mm 1.6 mm). *3 must not exceed pd or aso. operating conditions bd6903efv bd6904fp parameter symbol limit limit unit operating power supply voltage range vcc 4.5 5.5 4.5 5.5 v operating power supply voltage range vm 9 13.5 9 14 v operating power supply voltage range vg vm+3 19 vm+2 19 v uin, vin, win in-phase input voltage range vbemfd 0 vm - v com input in-phase voltage range vcomd - 0 vm-2.5 v pg amp in-phase input voltage range vpd 1.5 3.0 1.5 3.7 v
3/16 electrical characteristics bd6903efv (unless otherwise specified, ta=25 , vcc=5v, vm =12v, vg=17v) limit parameter symbol min. typ. max. unit conditions vcc total supply current icc - 9.2 14.2 ma vm total supply current 1 im1 - 1.4 2.8 ma lin=h or l vm total supply current 2 im2 - 1.4 2.8 ma lin=m high-side output saturation voltage voh - 0.4 0.8 v io=-400ma low-side output saturation voltage vol - 0.3 0.6 v io=400ma ec input bias current iec - 0.5 2 a torque reference start voltage vecr 2.35 2.5 2.65 v torque reference i/o gain gio 0.72 0.99 1.28 a/v ec=2.6v-2.7v gain output (hlm) rrnf = 0.5 ct1, ct2 charge current ictd -50 -35 -25 a ct1, ct2 discharge current icti 27 40 56 a high ct1, ct2 clamp voltage vcth 4.4 4.7 - v low ct1, ct2 clamp voltage vctl 0.8 1.0 1.3 v cst charge current icsth -20 -14 -6 a cst discharge current icsti 2 6 10 a high cst clamp voltage vcsth 2.4 2.8 3.3 v low cst clamp voltage vcstl 0.8 1.0 1.3 v input bias current ipg- - 0.1 0.25 a pg-=gnd dc bias current vpg 2.25 2.6 2.75 v pg-=pgout voltage gain 1 av1 17.5 18.8 - db f=1khz high output voltage vohp 3.4 3.75 v ioh=-1ma low output voltage volp - 1.2 1.6 v iol=1ma hysteresis width vhysp -75 -100 -125 mv high output voltage vpfgp 4.5 - - v io=-10 a middle output voltage vpfgm 2.25 - 2.75 v io= 10 a low output voltage vpfgl - - 0.5 v io=10 a high-level lin input vlinh 3.5 - - v loading: forward rotation middle-level lin input vlinm 2.35 - 2.65 v loading: brake low-level lin input vlinl - - 1.5 v loading: reverse rotation lin bias voltage vlinb 2.35 2.5 2.65 v output saturation voltage vce - 0.3 0.6 v io=200ma, total of output transistor high-side and low-side voltage source currents are treated as negative while sinking currents are treated as positive. this product is not designed to be resistant against radiation.
4/16 electrical characteristics bd6904fp (unless otherwise specified, ta=25 , vcc=5v, vm1=vm2 =12v, vg=17v) limit parameter symbol min. typ. max. unit conditions vcc total supply current icc - 9 13 ma high-side output saturation voltage voh - 0.4 0.7 v io=-300ma low-side output saturation voltage vol - 0.55 0.55 v io=300ma bemf comparator hysteresis width+ vhysb+ +24 +36 +48 mv bemf comparator hysteresis width- vhysb- -59 -43 -27 mv torque reference start voltage vecr 2.35 2.5 2.65 v torque reference i/o gain gio 0.80 1.05 1.33 a/v ec=2.3v-2.2v gain output (hlm) rrnf = 0.68 ? current limit voltage vcl 239 295 345 mv rrnf=0.68 ct1, ct2 charge current ictd -53 -39 -25 a ct1, ct2 discharge current icti 29 45 61 a high ct1, ct2 clamp voltage vcth 3.4 3.8 4.2 v low ct1, ct2 clamp voltage vctl 0.85 1.05 1.25 v cst charge current icsth -20 -14 -8 a cst discharge current icsti 2 5.5 9 a high cst clamp voltage vcsth 2.4 2.8 3.2 v low cst clamp voltage vcstl 0.8 1.0 1.2 v cst off voltage vcsto 3.6 3.8 4.0 v input bias current ipg- - 1 3 apg-=2.5v input offset voltage viop -8 - +8 mv dc bias current vpg 2.25 2.5 2.75 v pg-=pgout voltage gain 1 av1 50 71 - db f=1khz high output voltage vohp 3.4 3.75 - v ioh=-1ma low output voltage volp - 1.2 1.6 v iol=1ma pg detection level vpgth vbp-0.075 vbp-0.1 vbp-0.125 v high output voltage vpfgp 3.5 - - v io=-30 a middle output voltage vpfgm 2.1 - 2.9 v io= 10 a low output voltage vpfgl - - 0.9 v io=30 a high-level fin input vfinh 3.5 - - v high-level rin input vrinm 3.5 - - v low-level fin input vfinl - - 1.5 v low-level rin input vrinl - - 1.5 v output saturation voltage vce - 0.3 0.6 v io=200ma, total of output transistor high-side and low-side voltage source currents are treated as negative while sink currents are treated as positive. this product is not designed to be resistant against radiation.
5/16 reference data fig.4 loading output saturation voltage (total of high-side and low-side voltages) fig.1 total supply current (all blocks in operation) -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 output current [a] vm-output high voltage [v] -25 25 75 fig.2 drum output high-side saturation voltage 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 output curr ent [a] output low voltage [v] 75 25 -25 bd6903efv 0 2 4 6 8 10 01 234 5 vcc [v] circuit current : icc [ma] -25 25 75 operating range ( 4.5 5.5v ) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 200 400 600 800 1000 output current : io [ma] output voltage [v] -25 25 75 0.0 200.0 400.0 600.0 800.0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 ec voltag e [v] rnf current [ma] -25 25 75 fig.3 drum output low-side saturation voltage fig.5 torque reference gain (rnf = 0.5 ) fig.10 torque reference gain and current limit (rnf = 0.68 ? ) fig.6 total supply current (all blocks in operation) -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0 100 200 300 400 500 600 700 800 output curr ent [ma] vm-output high voltage [v] -25 25 75 fig.7 drum output high-side saturation voltage bd6904fp 0.0 100.0 200.0 300.0 400.0 500.0 2.0 2.1 2.2 2.3 2.4 2.5 2.6 ec voltag e [v] rnf current [ma] -25 25 75 0 2 4 6 8 10 01 234 5 vcc [v] circuit current : icc [ma] -25 25 75 operating range ( 4.5 5.5v ) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 100 200 300 400 500 600 700 800 output current [a] output low voltage [v] 75 25 -25 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 100 200 300 400 500 600 700 800 output current : io [ma] output voltage [v] -25 75 25 fig.8 drum output low-side saturation voltage fig.9 loading output saturation voltage (total of high-side and low-side voltages) operating range (4.5v~5.5v) operating range (4.5v~5.5v)
6/16 block diagram bd6903efv bd6904fp pin no. pin name function 1 gnd signal gnd pin 2 lin loading block logic input pin 3 ec torque reference control input 4 ct1 cylinder block slope capacitor connection pin 5 ct2 cylinder block slope capacitor connection pin 6 cst cylinder block startup oscillation capacitor connection pin 7 cnf cylinder block phase compensation capacitor connection pin 8 pgout cylinder block pgamp output pin 9 pg- cylinder block pg- input pin 10 vcc vcc pin 11 w cylinder block motor output pin 12 v cylinder block motor output pin 13 rnf cylinder block motor gnd pin (current detection resistor connection) 14 u cylinder block motor output pin 15 vg dmos vg power supply pin 16 vm cylinder and loading block motor power supply pin 17 out1 loading block motor output pin 18 out2 loading block motor output pin 19 lgnd loading block motor gnd pin 20 pfg pg/fg synthesis output pin pin no. pin name function 1 vm2 loading block motor power supply pin 2 out1 loading block motor output pin 3 lgnd loading block motor gnd pin 4 out2 loading block motor output pin 5 fin loading block logic input pin 6 rin loading block logic input pin 7 vg dmos vg power supply pin 8 gnd signal gnd pin 9 cst cylinder block startup oscillation capacitor connection pin 10 ct1 cylinder block slope capacitor connection pin 11 ct2 cylinder block slope capacitor connection pin 12 pci cylinder block phase compensation capacitor connection pin 13 cnf cylinder block phase compensation capacitor connection pin 14 ec torque reference control input pin 15 pg+ cylinder block pg+ input pin 16 pg- cylinder block pg ? input pin 17 pgout cylinder block pgamp output pin 18 pfg pg/fg synthesis output pin 19 vcc signal vcc pin 20 com cylinder block motor coil midpoint connection pin 21 vm1 cylinder block motor power supply pin 22 u cylinder block motor output pin 23 v cylinder block motor output pin 24 rnf cylinder block motor gnd pin (current detection resistor connection) 25 w cylinder block motor output pin drive signal th i selector pre-drive vm out2 out1 vcc lgnd pgfg synthesis startup control logic soft switch waveform tsd pre-drive control logic v u w rnf vg lin gnd pfg pgout pg- c 1 cst ct1 ct2 ec cnf vcc back emf detection comparator buffer output err amp cs amp vcc pg amp hysteresis comparator r 2 r 1 c 2 r a r b + + fig.11 1 10 f see p.10/16. 0.01 0.033 f see p.10/16. 0.01 0.033 f see p.10/16. 0.01 0.1 f see p.10/16. see p.10/16. 1 10 f see p.10/16. 0.4 1 see p.10/16. 1 10 f see p.10/16. drive signal selector pre-drive vm1 out2 out1 vcc lgnd pg fg synthesis startup control logic soft switch waveform tsd pre-drive control logic v u w rnf vg fin gnd pfgout pgout pg- cst ct1 ct2 ec cnf vcc low-side saturation prevention rin vm2 pg+ com pci err amp cs amp pg amp hysteresis comparator back emf detection comparator output + + c1 r1 r2 fig.12 1 10 f see p.10/16. 0.1 0.33 f see p.10/16. 0.01 0.033 f see p.10/16. 0.01 0.1 f see p.10/16. see p.10/16. 1 10 f see p.10/16. 0.01 0.1 f 0 500 see p.10/16. 1 10 f see p.10/16. 0.01 0.022 f see p.10/16. 1 10 f see p.10/16.
7/16 block operation cylinder motor driver block output phase selection operation (see figs.13 and 14 on p.9/16.) 1) back emf detection comparator the back emf detection comparator compares the motor output voltage and the motor midpoint potential to detect the position of the rotor (magnet) with respect to the stator (coil). for the bd6904fp, the motor's midpoint potential should be connect ed directly to the com pin, while for the bd6903efv, the midpoint of the resistor connected internally to the output is used as a proxy indicator of the motor's midpoint potential. 2) selector the selector selects either the internally synthesized 3-phase startup signal (startup mode) or back emf detection comparator output (back emf mode) based on the state of the sel. it then outputs the selected signal to the next block. the sel signal monitors the fg output and makes changes dependi ng on whether the motor is rotating or not. 3) drive signal synthesis the signals used in position detection ar e passed through the mask signal to eliminate any noise pulses caused by the motor's counter-electromotive voltage. these signals are then synthesized to create a signal (t he fg signal) that switches between high and low every 60 (electrical angle). after the pos ition detection signals have been subject to noise elimination, their phase is delayed 30 (electrical angl e) using the phase shift signal (compa). the signals are then synthesized with the slope signal to create trapezoidal wavefo rm signals that drive the high-side and lo w-side value of each of the u, v, and w-phase components. 4) soft switch waveform triangular waveforms are generated by c harging and discharging the capacitors connec ted to the ct1 and ct2 pins out of phase (ct2 is discharged while ct1 is c harged) using the fg signal. the mask si gnal, the phase shift signal (compa), and the slope signal are then created from these triangular waveforms. 5) pre-drive the pre-drive amplifies the u, v, and w-phase high-side and low- side drive trapezoidal waveform signals in proportion to the cs amp output signal. the voltage applied to the vg pin must be sufficiently higher than the vm voltage (bd6904fp: vm + 2 v or higher, bd6903efv: vm + 3 v or higher) in order to lower the on-resistance of the output's high-side power transistor. 6) output the signals from the pre-driver are curr ent-amplified and used to drive the motors. 7) startup control logic the charge/discharge cycle is repeated by connecting a capacitor to the cst pin. when the motor is stopped, the cst pin is discharged after being charged until it reaches the high cst clamp voltage (2.8v typ.). it charges again after reaching the low cst clamp voltage (1.0v typ.). this charge/discharge interval acts to generate a rectangular waveform, which becomes the sel signal. in addition to being input to the selector, the sel signal is used to generate the drive signal during startup. after its rising edge is divided, the sel si gnal is synthesized and output as the driv e signal during startup. when the sel sig nal is high, the selector selects the drive si gnal during startup to force the motor to rotate, generating the counter-electromotiv e voltage required for sensorless operation (synchronization mode) . once the motor starts rotating and the fg signal's rising edge is detected before the d.cst pin voltage reaches the hi gh cst clamp voltage, the cst pin begins to discharge in synchronization with the fg signal's risi ng edge. it then continues to repeat the cycl e, beginning to charge again when the low cst clamp voltage is reached and dischargi ng at the fg signal's rising edge. once sustained rotation is achieved, the sel signal will always be low because discharge occurs before the cs t pin voltage reaches the high cst clamp voltage, causing the selector to select the back emf comparator output signal to continue sensorless drive (back emf mode). output current control operation 1) cs amp. the rnf pin is connected to the cs amp's negative input, causin g a value (obtained by converting the output current to a voltage) to be input when a resistor with a small resistance value is connected between the rnf and gnd pins. the cs amp outputs a control signal to the pre-driver so that the posit ive input voltage and negative input voltage remain equal, causing a current, obtained by dividing the positive input voltage by the rnf resistance value, to flow to the motor. because this behavi or comprises a negative feedback loop, a phase-compensation capacitor must be connected to the cnf pin to prevent oscillation. 2) err amp. the err amp reduces the differential between the voltage input to the ec pin and the internal reference voltage by a fixed factor and outputs it to create the cs amp's positive input voltage. 3) low-side saturation prevention (bd6904fp only) the ic continuously monitors the voltage di fferential between the output pins and the rnf pin and controls the pins so that their voltage differential stays above an internally set level (s o that the output transistors do not become saturated). this c ontrol allows the ic to maintain the constant motor rotation by preventing distortion of the output current due to variations in the current's amplification factor caused by transistor saturation. because the low-side saturation prevention circuit comprises a negative feedback loop circuit, a phase-compens ation capacitor must be connected to the pci pin to prevent oscillation.
8/16 pg/fb waveform output operation (see fig.15 on p.9/16.) 1) pg amp, hysteresis comparator the pg amp amplifies the minute voltage generated by the motor's rotation in the external pg coil. the amp gain is determined by external resistors. the + input is biased through an internal reference. the hysteresis co mparator converts the pg amp output waveform to a noiseless rectangular waveform (the pg signal). 2) pg/fg synthesis the pg/fg synthesis circuit synthesizes the pg signal described above with the fg signal created by the drive signal synthesis circuit to output 3 values (high, middle, or low) to the pfg pin. the fg signal uses the low to middle output voltage , while the pg signal uses the middle to high output voltage. reversible motor driver 1) control logic the bd6903efv controls the output state based on 3-va lue signal that inputted to the lin pin (pin 2). the bd6604fp controls the output state based on 2-value signal t hat inputted to the fin pin (pin 5) and rin pin (pin6). the driver must be placed in open or brake mode wh enever switching between forward and reverse operation. for more information concerning the i/o logic, refer to the following table. tsd the tsd, or thermal shut-down circuit, turns off all driver output when the chip temperature tj reaches approximately 170c (typ, bd6903efv) or approximately 175c (typ, bd6904fp). the circ uit resets after approximately 20c (typ, bd6903efv) or 25c (typ, bd6904ep) of hysteresis. loading block i/o logic table bd6903efv when no voltage is applied to v cc , the loading block output and cylinder block output are open. bd6904fp when no voltage is applied to v cc , the loading block output and cylinder block output are open. lin out1 out2 mode h h l forward rotation m l l short brake l l h reverse rotation fin rin out1 out2 mode h l h l forward rotation l h l h reverse rotation h h l l short brake l l open open standby
9/16 timing chart block waveforms during back emf mode operation startup waveforms pg/fg synthesis u v w bemf_u bemf_v bemf_w bemf_u after noise elimination fg ct1 ct2 slope comp a mask uh ul vh vl wh wl iu iv iw bemf_v after noise elimination bemf_w after noise elimination fig.13 fig.14 cst sel reset vcc qu qv qw fg h m l fg pgout pfg hysteresis comparator output fig.15 hysteresis width
10/16 selecting application components 1) cst pin the cst pin outputs a triangular waveform when a capacitor is connected between the cst and gnd pins. the synchronized signal period and back emf signal detection time varies with the connected capacitance value. select the optimum value that produces t he shortest startup time for the motor being used. for most sensorless motors, a value between 0.1 f and 0.33 f is ideal. 2) ct1, ct2 pins the ct1 and ct2 pins output triangular waveforms when capaci tors are connected between the ct1 and gnd pins and the ct2 and gnd pins. these triangular waveforms ar e synchronized to the fg signal's hi gh and low changes to create a repeating charge/discharge cycle. the triangular waveforms output by the ct1 and ct2 pins are anti-phase relative to one another. ct1 and ct2 are reached to vctl (low ct1, ct2 clamp voltage - see pgs. 3 and 4) to enable large discharge currents. both the mask signal, which is used to reject the noi se pulse caused by the motor's back emf, and the slope signal, used to apply a grad ient when the output current changes, are generated from the ct1 and ct2 triangular waveforms. the amount of phase shift occurring from the rotor position detecti on comparator to the output voltage varies with the capacita nce value connected to the ct1 and ct2 pins, as does the mask signal time width. the gradient applied when the output current changes als o varies accordingly. connect the same capacitance value to bot h the ct1 and ct2 pins. the optimum value should be selected according to the motor being used so that there are no problems with motor rotation, output voltage, etc. for most sensorless motors, a value from 0.01 f to 0.033 f is ideal. 3) cnf pin the cnf pin serves as the cs amp output. the connection of a capacitor between it and the gnd pin enables phase compensation. the capacitance value should be selected bas ed on the servo constant, and proper motor operation should be confirmed. when the capacitance is too high, the i/o response deteriorates, wh ile when too low, the output becomes easy to oscillate. a value between 0.01 f and 0.1 f is ideal. 4) rnf pin connecting a resistor between the rnf and gnd pins allows the detection of the current value flowing to output. the output current io is determined using the following equati on, where rnf denotes the resistance connected between the rnf an d gnd pins, and vec denotes the voltage applied to the ec pin. io (vec vecr) ? gio ? 0.5/rnf (a) bd6903efv io (vecr vec) ? gio ? 0.68/rnf (a) bd6904fp (vecr: torque reference start voltage, gio: torque reference i/o gain ? see p. 3/16, p. 4/16) the bd6904fp incorporates a built-in current limiting circuit. the current limit curr ent iomax is determined by the following e quation: iomax vcl/rnf (a) vcl: current limit voltage - see p. 4/16 for the bd6903efv, a value from 0.4 to 1 (typical value: 0.5 ) is recommended. for the bd6904fp, a value from 0.45 to 1 (typical value: 0.68 ) is recommended. 5) motor output u, v, and w pins (applies to bd6904fp) when there is a large amount of output voltage noise, reduce the noise by connecting a capacitor a nd resistor in series between each output pin and the com pin. determine the appropriate constants ba sed on the motor. use of non-optimum values may result in sta rtup failures or uneven rotation. if the motor operates properly without the capacitor and resistor, there is no need to add them. the optimum capacitance and resistance values are from 0.01 f to 0.1 f and 0 to 500 , respectively. 6) pg amp gain setting resistance and filter capacitance the pg amp gain gpg is determined by the ratio of r1 to r2 as described in the following equation: gpg=20logr2/r1 (db) set the gain from the input signal level so that the pgout am plitude is large enough compared to the hysteresis comparator's hysteresis level (bd6903efv: vhysp - see p. 3/16, bd6904fp: vpgth - see p. 3/16) and so that the high and low output voltages (vohp, volp: see p. 3/16) are not clamped. r1 and c1 form a high-pass filter, while r2 and c2 form a low-pass filter, with the respective cutoff frequencies f hpf and f lpf determined by the following equation: f hpf =1/2 r1c1, f lpf =1/2 r2c2 select a value for which the main pg signal is not attenuated by the motor but for which unnecessary noise is attenuated. 7) pg coil bias resistance (applies to bd6903efv), pg+ pin (applies to bd6904fp) a dc bias is applied to the pg coil due to the pg coil's bias re sistance. set ra = rb to enable common mode rejection for the p g amp's positive input and vcc fluctuations. sele ct resistance values such that the current flowing to ra and rb is small and not prone to other types of interference. if the pg+ pin is affected by noise, connect a ca pacitor between the pg+ pin and the gnd pin. the optimum resistance and capacitance values are from 10k to 100k and 0.01 f to 0.33 f, respectively. 8) vcc, vm, vg pins select a capacitance value that can su fficiently suppress high-frequency noise. a value between 1 f and 10 f is ideal.
11/16 board layout precautions 1. v cc (bd6903efv: pin 10, bd6904fp: pin 19) and vg pins (bd6903efv: pin 15, bd6904fp: pin 7) internal circuits other than outp ut transistors operate on the v cc and vg power supplies. the introduction of noise from an external source on these power supply lines may cause the ic to malfunction. patterns should be laid out so that they are not affected b y noise. 2. gnd pin (bd6903efv: pin 1, bd6904fp: pin 8) use the thickest wiring possible for ground. 3. power output pin (bd6903efv: pins 11, 12, 14, 17, and 18; bd6904fp: pins 2, 4, 22, 23, and 25) power loss may occur due to wiring resistance. therefore, the ic should be placed close to t he motor and connected using the sh ortest, thickest wiring possible. 4. motor gnd pin (bd6903efv: pins 13 and 19, bd6904fp: pins 3 and 24) use the thickest wiring possible to prev ent resistance contribution from the wiri ng. connect the pin to the application ground using a separate line. 5. com pin (applies to bd6904fp: pin 20) use caution as noise input to the ic 's internal back emf detection comparat or will cause the ic to malfunction. 6. ct1, ct2 pins (bd6903efv: pins 4 and 5, bd6904fp: pins 10, and 11) use wiring of the same length and place the 2 capacitors close to the pins to ensure that they have the same charging/dischargi ng characteristics. 7. pg amp (bd6903efv: pins 8 and 9, bd6904fp: pins 15,16 and 17) noise will cause the ic to malfunction. position the pg coil, exte rnal capacitors, and external resistors as close as possible to their respective pins. 8. island (applies to bd6903efv) connect the island to the gnd pin using a separa te line made of the thickest wiring possible. power dissipation reduction the power dissipation (all loss) of the ic s hows the power consumption of the ic when the ambient temperature is at room temper ature (ta = 25c). the ic will generate heat when the ic consumes power, causing the temperature of the ic chip to be higher than the ambient temperature. the power consumption of the ic is limit ed. the power dissipation is determined by the thermal resistance (heat dissipation characteristics) of the package and the permissible temperature (i.e. absol ute maximum rating of the junction tempe rature) of the ic chip in the package. heat generated as a result of power consumption is radiated from the mold resin or lead frame of the package. a parameter that hampers the thermal radiation performance is called thermal resistance and expressed by j-a [c/w]. the ic temperature in the package can be determined from the thermal resistance. fig.16 depicts a thermal resistance package model. the thermal resistance j-a, ambient temperature ta, junction temperature tj, and power consumption p are obtained from the following equation. ja (tj ta ) / p [ /w] ( ) the heat mitigation curve (derating curve) in figs. 38 and 39 sh ows the permissible power consumption of the ic at ambient temperature. the possible power consumption of the ic decreases with increases in am bient temperature. this slope is determined by the thermal resistance ja. the thermal resistance ja depends on a variety of conditions, such as t he chip size, power consumption, package ambient temperature, mounting conditions, and wind velocity. the derati ng curve depicts the reference va lues measured under specific conditions. for the bd6903efv, the power dissipation is derated by 8.0 mw/ over 25c when mounted on a glass epoxy board (70 mm 70 mm 1.6 mm). for the bd6904fp, it is reduced by 11.6 mw/c over 25c when mounted on a glass epoxy board (90 mm 90 mm 1.6 mm). fig.16 thermal resistance ja = (tj-ta) / p [ /w] package surface temperature ta[ ] a mbient temperature ta[ ] chip surface temperature tj[ ] power consumption p[w]
12/16 heat loss 1) heat generation mechanism with the bd6903efv and bd6904ep, heat generation requires special a ttention during startup. heat generation is significantly af fected by the output current io the high-side and low-side loss voltage, as illustrated in equation (1) below. the load on the ic is further increased when used with motors with low impedances,. the ic's power consumption p is expressed by equation (1). p=vcc icc d.io d.vloss l.io l.vloss (1) (d.io d.vloss cylinder block power consumption, l.io l.vloss loading block power consumption) consider equation (1) as well as the pack age power (pd) and ambient temperature (ta) during operation and confirm that the ic's chip temperature tj does not exceed 150c. the chip will cease to function as a se miconductor when tj exceeds 150c, and problem s such as parasitic behavior and leaks wil l occur. continued use of the chip under these conditions will re sult in ic deterioration and damage. therefore, the junction tem perature must not exceed tjmax=150 under any circumstances. 2) measuring the chip temperature the chip temperature can be determined by the following measurements. when not using the pfg output pin, the chip temperature can be estimated using the internal diode' s temperature characteristics. when calculating the chip temperature x under a given set of conditions: potential a (mv) at tj = 25c potential b (mv) at tj = xc for example, if the value -2(mv/c) is used for the diode?s temperature characteristics, the chip temperature is given by: if an accurate chip temperature is required, the temperature char acteristics of all of the ic's internal diodes must be taken i nto account. b a [mv] 2 [mv / c] 25=x(c) pfg gnd fig.17 motor output circuit diagram spvm1, 2 io output high-side and low-side loss voltage vloss=voh+vol fig.18 output waveform vm rnf lgnd high-side loss voltage voh output waveform low-side loss voltage vol internal equivalent circuit v 100 a sink a constant-current of 100
13/16 i/o equivalent circuit diagrams 1) loading block logic input pin 2) torque reference control input pin bd6903efv bd6904fp 3) slope capacitor connection pin 4) star tup oscillation capacitor connection pin bd6903efv bd6904fp bd6903efv bd6904fp 5) capacitor connection pin for phase co mpensation 6) pgout output, pg input bd6903efv bd6904fp bd6903efv 7) cylinder block motor output bd6904fp u, v, w rnf * 8) loading block motor output 9) pg/fg synthesis output 10) dmos vg power supply out1 ,out2, lgnd ct1 1k 1k ct2 ???? ???? vcc cst cnf vcc 250 6k 2k 6k 6k pg- 6k 6k 25k 25k pgout . 30 30 vcc u 30k v 30k w vm rnf 30k ? 4.7k 4.7k 4.7k u 20k 20k 20k v w vm 20k 20k 20k vm out1 out2 lgnd pfg 4.8k 10 5k vcc fin 70k 1k vcc rin ct1 1k 1k ct2 ???? 6k bias vcc ?? vcc cst 70 6k pg- 6k vcc 25k 25k pgout 30 30 vcc pg+ fig.21 to differential amp input ec(3pin) 6k 6k fig.22 fig.23 fig.25 fig.26 fig.27 fig.29 fig.30 fig.31 fig.32 fig.33 fig.34 lin 6k vcc 33k fig.20 33k fig.24 6k u pci bias 6k 6k v 6k w fig.28 vg loading block high-side output pre-driver fig.35 cylinder block high-side output pre-driver to differential amp inputs to differential amp inputs to differential amp to differential amp to differential amp input to virtual midpoint
14/16 operation notes (1) absolute maximum ratings an excess in the absolute maximum ratings, such as supply voltag e, temperature range of operating conditions, etc., can break d own the devices, thus making impossible to ident ify breaking mode, such as a short circui t or an open circuit. if any over rated va lues will expect to exceed the absolute maximu m ratings, consider adding circuit protection devices, such as fuses. ( 2 ) connecting the power supply connector backward connecting of the power supply in reverse polarity can damage ic. take precautions when connecting the power supply lines. an external direction diode can be added. ( 3 ) power supply lines design pcb layout pattern to provide low impedance gnd and su pply lines. to obtain a low noise ground and supply line, separate the ground section and supply lines of the digital and analog blocks. furthermore, for all power supply terminals to ics, connect a capacitor between the power supply and the gnd termi nal. when applying electrolytic capacitors in the circuit, note that capacitance characteristic values are re duced at low temperatures. ( 4 ) gnd voltage the potential of gnd pin must be minimum potential in all operating conditions. ( 5 ) thermal design use a thermal design that allows for a sufficient margin in li ght of the power dissipation (pd) in actual operating conditions. ( 6 ) inter-pin shorts and mounting errors use caution when positioning the ic for mount ing on printed circuit boards. the ic ma y be damaged if there is any connection er ror or if pins are shorted together. ( 7 ) actions in strong electromagnetic field use caution when using the ic in the pr esence of a strong electromagnetic field as doing so may cause the ic to malfunction. ( 8 ) aso when using the ic, set the output transistor so that it does not exceed absolute maximum ratings or aso. ( 9 ) thermal shutdown circuit the ic incorporates a built-in thermal shutdown circuit (tsd circ uit). the thermal shutdown circ uit (tsd circuit) is designed o nly to shut the ic off to prevent thermal runaway. it is not designed to pr otect the ic or guarantee its operation. do not continue to use the ic after operating this circuit or use the ic in an environment where the operati on of this circuit is assumed. tsd on temperature [c] (typ.) hysteresis temperature [c] (typ.) bd6903efv 170 20 bd6904fp 175 25 ( 10 ) testing on application boards when testing the ic on an application board, connecting a capacitor to a pin with low impedance subjects the ic to stress. alwa ys discharge capacitors after each process or step. always turn t he ic's power supply off before connecting it to or removing it f rom a jig or fixture during the inspection process. ground the ic during assembly steps as an antista tic measure. use si milar precaution whe n transporting or storing the ic.
15/16 ( 11 ) regarding input pin of the ic this monolithic ic contains p+ isolati on and p substrate layers between adjacent el ements in order to keep them isolated. p-n junctions are formed at the intersection of these p layers with the n laye rs of other elements, creating a parasitic diode or transistor. for example, the relation between each potential is as follows: when gnd > pin a and gnd > pin b, the p-n junction operates as a parasitic diode. when gnd > pin b, the p-n junction oper ates as a parasitic transistor. parasitic diodes can occur inevitable in the structure of the ic . the operation of parasitic diodes can result in mutual interf erence among circuits, operational faults, or physical damage. accordingly, methods by which parasitic diodes operate, such as applying a vo ltage that is lower than the gnd (p substrate) vo ltage to an input pin, should not be used. (12 ) ground wiring pattern when using both small signal and large current gnd patterns, it is recommended to isolate the two ground patterns, placing a si ngle ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by larg e currents do not cause variations in the small signal ground voltage. be careful not to change the gnd wiring pattern of any external com ponents, either. (13) power supply activation sequence the power supplies should be turned on in a specific order: vm vg vcc. likewise, they should be turned off in a particular order: vcc vg vm. the position of vg and vm in the order can be switched without causing a problem. however, if vcc is activated before vm and vg have been turned on , the loading block logic input pin (bd 6903efv: pin 2, bd6904fp: pins 5 and 6) mu st be open and the torque reference control input pins (bd6903efv: pin 3, bd6904fp: pin 14) set to 0v. also, when vm and vg are turned off before vcc, the loading block logic input pin (bd 6903efv: pin 2, bd6904fp: pins 5 and 6) must be open. when turning the power supplies on/off without regard to the or ders described above, it is recommended that the loading block l ogic input pin (bd6903efv: pin 2, bd6904fp: pins 5 and 6) be open and the torque reference control input pins (bd6903efv: pin 3, bd6904fp: pin be set to 0v. power dissipation reduction bd6903efv bd6904fp ta [ ] 2.0 pd[ ] 1.0 0 150 125 100 75 50 25 ta [ ] 2.0 1.45 pd[ ] 1.0 0 150 125 100 75 50 25 * reduced by 8.0 mw/c over 25c when mounted on a glass epoxy board (70 mm 70 mm 1.6 mm). fig.37 * reduced by 11.6 mw/c over 25c when mounted on a glass epoxy board (90 mm 90 mm 1.6 mm) fig.38 fig. 36 example of ic structure resistor transistor (npn) n n n p + p + p p substrate gnd parasitic element pin a n n p + p + p p substrate gnd parasitic element pin b c b e n gnd pin a p aras iti c element pin b other adjacent elements e b c gnd p aras iti c element
catalog no.05t348be '05.10 rohm c 1000 tsu ? please verify and specify the entire part number when ordering. part number explanation b d 6 9 0 3 e D e 2 f e1: reel-wound embossed taping, pin 1 at front e2: reel-wound embossed taping, pin 1 at back part number ? bd6903efv ? bd6904fp package type ? efv ? fm :htssop-b20 : hsop25 v direction of feed hsop25 (unit: mm) 7.8 0.3 5.4 0.2 2.75 0.1 1.95 0.1 25 14 1 13 0.11 1.9 0.1 0.36 0.1 0.3min. 0.25 0.1 13.6 0.2 0.8 0.1 tape quantity direction of feed embossed carrier tape 2000pcs (pin 1 is at the upper left when holding the reel with the left hand while pulling the tape with the right.) e2 reel pin 1 1234 1234 1234 1234 1234 1234 1234 please order in multiples of the minimum package quantity. unit: mm) htssop-b20 1.0max. 10 1 20 11 0.17 1.0 0.2 0.5 0.15 0.65 s 0.08 + 0.05 ? 0.04 + 0.05 ? 0.03 0.2 6.4 0.2 0.85 0.05 0.08 0.05 4.4 0.1 0.325 6.5 0.1 s direction of feed ta p e quantit y direction of feed embossed carrier ta p e 2500 p cs e2 (pin 1 is at the upper left when holding the reel with the left hand while pulling the tape with the right) reel pin 1 1234 1234 1234 1234 please order in multiples of the minimum package quantity. 1234 1234 1234 1234
notes no technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of rohm co.,ltd. the contents described herein are subject to change without notice. the specifications for the product described in this document are for reference only. upon actual use, therefore, please request that specifications to be separately delivered. application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. rohm co.,ltd. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by rohm co., ltd. is granted to any such buyer. products listed in this document are no antiradiation design. appendix1-rev2.0 thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact your nearest sales office. rohm customer support system the americas / europe / asia / japan contact us : webmaster@ rohm.co. jp www.rohm.com copyright ? 2008 rohm co.,ltd. the products listed in this document are designed to be used with ordinary electronic equipment or de vices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of which would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. it is our top priority to supply products with the utmost quality and reliability. however, there is always a chance of failure due to unexpected factors. therefore, please take into account the derating characteristics and allow for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in order to prevent possible accidents that may result in bodily harm or fire caused by component failure. rohm cannot be held responsible for any damages arising from the use of the products under conditions out of the range of the specifications or due to non-compliance with the notes specified in this catalog. 21 saiin mizosaki- cho, ukyo-ku, kyoto 615-8585, japan tel : +81-75-311-2121 fax : +81-75-315-0172 appendix

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